2011

Software Co-Verification Based on Program Traces from Different Processors

Robledo Alencar, Sandro Rigo, Rodolfo Azevedo. In 3rd Workshop on Infrastructures for Software/Hardware co-design - WISH. Charmonix, France. 2011.

A HW/SW Co-designed Heterogeneous Multi-core Virtual Machine for Energy-Efficient General Purpose Computing

Youfeng Wu, Shiliang Hu, Edson Borin, Cheng Wang. In Code Generation and Optimization (CGO), 2011 9th Annual IEEE/ACM International Symposium on. p. 236-245. 2011.

LAR-CC: Large Atomic Regions with Conditional Commits

Edson Borin, Youfeng Wu, Mauricio Breternitz Jr., Cheng Wang. In Code Generation and Optimization (CGO), 2011 9th Annual IEEE/ACM International Symposium on. p. 54--63. 2011.

LUTS: A Lightweight User-Level Transaction Scheduler

Daniel Nicácio, Alexandro Baldassin, Guido Araújo. In Algorithms and Architectures for Parallel Processing. v. 7016. p. 144-157. 2011.

Using multiple abstraction levels to speedup an MPSoC virtual platform simulator

J. Moreira, F. Klein, A. Baldassin, P. Centoducatte, R. Azevedo, S. Rigo. In Rapid System Prototyping (RSP), 2011 22nd IEEE International Symposium on. p. 99 -105. 2011.

Live Range Hole Allocation in Dynamic Binary Translation

Wesley Attrot, Daniel Nicacio, Edson Borin, Sandro Rigo, Guido Araujo. In 4th Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT'11, 2011.. San Jose, USA. 2011.

Structure-Constrained Microcode Compression

Edson Borin, Guido Araujo, Mauricio Breternitz Jr., Youfeng Wu. In 23rd Symposium on Computer Architecture and High Performance Computing. p. 104-111. 2011.

2010

Versatile system-level memory-aware platform description approach for embedded MPSoCs

Robert Pyka, Felipe Klein, Peter Marwedel, Stylianos Mamagkakis. In LCTES '10: Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems. p. 9--16. Stockholm, Sweden. 2010.

Optimizing a Retargetable Compiled Simulator to Achieve Near-Native Performance

M.S. Garcia, R. Azevedo, S. Rigo. In 11th Symposium on Computing Systems (WSCAD-SCC). p. 33 -39. 2010.

ISAMAP: Instruction Mapping Driven by Dynamic Binary Translation

Maxwell Souza, Daniel Nicarcio, Guido Araujo. 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT'10, 2010.. 2010.

Trace Execution Automata in Dynamic Binary Translation

Joao Porto, Guido Araujo, Edson Borin, Youfeng Wu. 3rd Workshop on Architectural and Microarchitectural Support for Binary Translation, AMAS-BT'10, 2010.. 2010.

Integer-linear Formulation for the DAGs-packing Problem

Rubia Santos, Rodolfo Azevedo, Ricardo Santos. In INFORMS Joint International Meeting Book of Abstracts. p. 34. 2010.

STM versus lock-based systems: an energy consumption perspective

Felipe Klein, Alexandro Baldassin, Joao Moreira, Paulo Centoducatte, Sandro Rigo, Rodolfo Azevedo. In ISLPED '10: Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design. p. 431--436. Austin, Texas, USA. 2010.

T-DRE: a hardware trusted computing base for direct recording electronic vote machines

Roberto Gallo, Henrique Kawakami, Ricardo Dahab, Rafael Azevedo, Saulo Lima, Guido Araujo. In Proceedings of the 26th Annual Computer Security Applications Conference. p. 191--198. Austin, Texas. 2010.

ARP: Um Gerenciador de Pacotes para Sistemas Embarcados com Processadores Modelados em ArchC

Rodolfo Azevedo, Bruno Albertini, Sandro Rigo. In Workshop de Sistemas Embarcados - WSE. Gramado. 2010. (In Portuguese)

2009

Dotando ArchC com infraestrutura para geração de montadores e simuladores ARM

Rafael Auler, Paulo Centoducatte. In WSCAD-WIC '09: X Simpósio em Sistemas Computacionais - Workshop de Iniciação Científica. São Paulo, Brazil. 2009. (In Portuguese)

A Multi-Model Engine for High-Level Power Estimation Accuracy Optimization

F. Klein, R. Leao, G. Araujo, L. Santos, R. Azevedo. Very Large Scale Integration (VLSI) Systems, IEEE Transactions on. v. 17. p. 660 -673. 2009.

Improving Accuracy in Power Estimation by Exploiting Multi-Model Techniques

Felipe Klein, Guido Araujo, Rodolfo Azevedo. In VLSI-Soc 2009 (PhD Forum): Proceedings of the 17th IFIP/IEEE International Conference on Very Large Scale Integration (PhD Forum). 2009.

Estimativa de Consumo de Energia em Nível de Instrução para Processadores Modelados em ArchC

Josue Ma, Rodolfo Azevedo. In Workshop de Sistemas Computacionais - WSCAD-SSC. p. 119-126. São Paulo. 2009. (In Portuguese)

Um sistema de ligação dinâmica independente de arquitetura baseado em ADL

Rafael Auler, Paulo Cesar Centoducatte, Alexandro Baldassin. Technical Report: Institute of Computing, University of Campinas. 2009. (In Portuguese)

A pattern based instruction encoding technique for high performance architectures

Ricardo Santos, Rafael Batistella, Rodolfo Azevedo. International Journal of High Performance Systems Architecture. v. 2. p. 71-80. 2009.

Comparing RTL and high-level synthesis methodologies in the design of a theora video decoder IP core

L. Piga, S. Rigo. Programmable Logic, 2009. SPL. 5th Southern Conference on. p. 135 -140. 2009.

Characterizing the Energy Consumption of Software Transactional Memory

Alexandro Baldassin, Felipe Klein, Guido Araujo, Rodolfo Azevedo, Paulo Centoducatte. Computer Architecture Letters. v. 8. p. 56-59. 2009.

HW/SW co-design of Identity-Based Encryption using a custom instruction set

L. Amaral, G. Araujo, J. Lopez. International Conference on Field-Programmable Technology, 2009. FPT 2009.. p. 510 -513. 2009.

SPARC16: A New Compression Approach for the SPARC Architecture

Leonardo Luiz Ecco, Bruno Cardoso Lopes, Eduardo Candido Xavier, Ricardo Pannain, Paulo Centoducatte, Rodolfo Jardim de Azevedo. In SBAC-PAD '09: Proceedings of the 2009 21st International Symposium on Computer Architecture and High Performance Computing. p. 169--176. 2009.

On the Energy-Efficiency of Software Transactional Memory

F. Klein, A. Baldassin, G. Araujo, P. Centoducatte, R. Azevedo. In SBCCI '09: Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design. p. 1--6. Natal, Brazil. 2009.

2008

Abstract Cold Code Analysis

Wesley Attrot. In AMAS-BT: Proceedings of 1th Workshop on Architectural and Microarchitectural Support for Binary Translation. p. 14-21. Beijing, China. 2008.

PBIW: Uma Codificação de Instruções Alternativa para Arquiteturas de Alto Desempenho

Rafael Batistella, Ricardo Santos, Rodolfo Azevedo. In WSCAD-SSC Simpósio em Sistemas Computacionais. p. 151-158. 2008.

Design, Implementation and Evaluation of two MP3 Hardware Decoder in Different Abstraction Levels using SystemC

F. Goldstein, R. Azevedo. In Design & Verification Conference. San Jose, CA, USA. 2008.

An Instruction Scheduling Algorithm Based on Subgraph Isomorphism

R. Santos, R. Azevedo. In Simpósio Brasileiro de Linguagens de Programação. Fortaleza, CE, Brasil. 2008. (In Portuguese)

Instruction Scheduling Based on Subgraph Isomorphism for a High Performance Computer Processor

R. Santos, R. Azevedo, G. Araujo. Journal of Universal Computer Science. v. 14. p. 3465--3480. 2008.

A Software Transactional Memory System for an Asymmetric Processor Architecture (Best Paper Award)

Felipe Goldstein, Alexandro Baldassin, Paulo Centoducatte, Rodolfo Azevedo, Leonardo A. G. Garcia. In SBAC-PAD '08: Proceedings of the 2008 20th International Symposium on Computer Architecture and High Performance Computing. p. 175--182. 2008.

2007

A DAGs-Packing Heuristic for a High Performance Processor Architecture

Ricardo Santos, Rodolfo Azevedo, Rubia Oliveira. In XXXIX Simpósio Brasileiro de Pesquisa Operacional. 2007.

Automatic Retargeting of Binary Utilities for Embedded Code Generation

Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel Casarotto, Luiz C. V. Santos, Max Schultz, Olinto Furtado. In ISVLSI '07: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. p. 253--258. 2007.

A Methodology and Toolset to Enable SystemC and VHDL Co-simulation

Richard Maciel, Bruno Albertini, Sandro Rigo, Guido Araujo, Rodolfo Azevedo. VLSI, IEEE Computer Society Annual Symposium on. v. 0. p. 351-356. 2007.

An Efficient Framework for High-Level Power Exploration

F. Klein, G. Araujo, R. Azevedo, R. Leao, dos Luiz Santos. In MWSCAS 2007: Proceedings of the 50th Midwest Symposium on Circuits and Systems. p. 1046-1049. 2007.

On the Limitations of Power Macromodeling Techniques

Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz C. V. Dos Santos. In ISVLSI 2007: Proceedings of the IEEE Computer Society Annual Symposium on VLSI. p. 395-400. 2007.

A Multi-Model Power Estimation Engine for Accuracy Optimization

Felipe Klein, Guido Araujo, Rodolfo Azevedo, Roberto Leao, Luiz Santos. In ISLPED '07: Proceedings of the 2007 international symposium on Low power electronics and design. p. 280--285. Portland, OR, USA. 2007.

A Flexible Platform Framework for Rapid Transactional Memory Systems Prototyping and Evaluation

Fernando Kronbauer, Alexandro Baldassin, Bruno Albertini, Paulo Centoducatte, Sandro Rigo, Guido Araujo, Rodolfo Azevedo. In RSP '07: Proceedings of the 18th IEEE/IFIP International Workshop on Rapid System Prototyping. p. 123--129. 2007.

PowerSC: A SystemC Framework for Power Estimation

F. Klein, G. Araujo, R. Azevedo. In 6th NASCUG, San Jose, USA. 2007.

PowerSC: A SystemC-based Framework for Power Estimation

Felipe Klein, Roberto Leao, Guido Araujo and Luiz Santos, Rodolfo Azevedo. Technical Report: Institute of Computing, University of Campinas. 2007.

2006

The 2D-VLIW Architecture

Ricardo Santos, Rodolfo Azevedo, Guido Araujo. Technical Report: Institute of Computing, University of Campinas. 2006.

Exploiting dynamic reconfiguration techniques: the 2D-VLIW approach

R. Santos, R. Azevedo, G. Araujo. 20th International Parallel and Distributed Processing Symposium, 2006. IPDPS 2006. p. 4 pp.. 2006.

Projeto e Desenvolvimento de Sistemas Embarcados Multiprocessados

Rodolfo Azevedo, Sandro Rigo, Guido Araujo. Atualizações em Informática. p. 331 -386. 2006. (In Portuguese)

Dual Selective Code Compression

Eduardo Bráulio Wanderley Netto, Eduardo Billo, Rodolfo Jardim Azevedo. XXXII Conferência Latino Americana de Informática, 2006. 2006.

Software-Based Transparent and Comprehensive Control-Flow Error Detection

Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo. In CGO '06: Proceedings of the International Symposium on Code Generation and Optimization. p. 333--345. 2006.

2D-VLIW: An Architecture Based on the Geometry of Computation

Ricardo Santos, Rodolfo Azevedo, Guido Araujo. International Conference on Application-specific Systems, Architectures and Processors, 2006. ASAP '06. p. 87 -94. 2006.

Clustering-Based Microcode Compression

E. Borin, M. Breternitz, Youfeg Wu, G. Araujo. International Conference on Computer Design, 2006. ICCD 2006. p. 189 -196. 2006.

2005

Platform designer: An approach for modeling multiprocessor platforms based on SystemC

Cristiano Araujo, Millena Gomes, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Araujo. Design Automation for Embedded Systems. v. 10. p. 253-283. 2005.

Exploiting the Area X Performance Trade-off with Code Compression

E.W. Netto, E. Billo, R. Azevedo. International Symposium on System-on-Chip, 2005. p. 42 -45. 2005.

High-Level Switching Activity Prediction Through Sampled Monitored Simulation

F. Klein, R. Azevedo, G. Araujo. International Symposium on System-on-Chip, 2005. p. 161 -166. 2005.

A SystemC-only design methodology and the CINE-IP multimedia platform

Guido Araújo, Edna Barros, Elmar Melcher, Rodolfo Azevedo, Karina Silva, Bruno Prado, Manoel Lima. Design Automation for Embedded Systems. v. 10. p. 181-202. 2005.

Geração Automática de Montadores para Modelos de Arquiteturas Escritos em ArchC

A. Baldassin, P.C. Centoducatte. In Proceedings of the 9th Brazilian Symposium on Programming Languages. p. 36 - 49. 2005.

A custom instruction approach for hardware and software implementations of finite field arithmetic over F2163 using Gaussian normal bases

M. Juliato, G. Araujo, J. Lopez, R. Dahab. IEEE International Conference on Field-Programmable Technology. p. 5 - 12. 2005.

Efficient datapath merging for partially reconfigurable architectures

N. Moreano, E. Borin, Cid de Souza, G. Araujo. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v. 24. p. 969 - 980. 2005.

Design of a Decompressor Engine on a SPARC Processor

E. Billo, R. Azevedo, G. Araujo, P. Centoducatte, E.W. Netto. 18th Symposium on Integrated Circuits and Systems Design. p. 110 -114. 2005.

Dynamic binary control-flow errors detection

Edson Borin, Cheng Wang, Youfeng Wu, Guido Araujo. SIGARCH Comput. Archit. News. v. 33. p. 15--20. 2005.

Enabling High-Level Switching Activity Estimation using SystemC

F. Klein, R. Azevedo, G. Araujo. Technical Report: Institute of Computing, University of Campinas. 2005.

Processor Centric Specification and Modelling of MPSoCs

Cristiano C. de Araujo and Edna Barros and Rodolfo Azevedo and Guido Araujo. In Forum on specification and Design Languages. p. 303-315. 2005.

Extending the ArchC language for automatic generation of assemblers

A. Baldassin, P.C. Centoducatte, S. Rigo. 17th International Symposium on Computer Architecture and High Performance Computing. SBAC-PAD 2005. . p. 60 - 67. 2005.

The datapath merging problem in reconfigurable systems: Complexity, dual bounds and heuristic evaluation

Cid C. de Souza, Andre M. Lima, Guido Araujo, Nahri B. Moreano. J. Exp. Algorithmics. v. 10. p. 2.2. 2005.

The ArchC Architecture Description Language and Tools

Rodolfo Azevedo, Sandro Rigo, Marcus Bartholomeu, Araujo, Guido, Cristiano Araujo, Edna Barros. International Journal of Parallel Programming. v. 33. p. 453-484. 2005.

2004

An automatic testbench generation tool for a systemC functional verification methodology

K.R.G. da Silva, E.U.K. Melcher, G. Araujo. In 17th Symposium on Integrated Circuits and Systems Design, 2004 - SBCCI 2004. p. 66 - 70. 2004.

Multi-profile instruction based compression

E.W. Netto, R. Azevedo, P. Centoducatte, G. Araujo. In 16th Symposium on Computer Architecture and High Performance Computing, 2004 - SBAC-PAD 2004. p. 23 - 29. 2004.

The Datapath Merging Problem in Reconfigurable Systems: Lower Bounds and Heuristic Evaluation

Cid C. de Souza, André M. Lima, Nahri Moreano, Guido Araujo. In Experimental and Efficient Algorithms. v. 3059. p. 545-558. 2004.

The design of dynamically reconfigurable datapath coprocessors

Zhining Huang, Sharad Malik, Nahri Moreano, Guido Araujo. ACM Trans. Embed. Comput. Syst.. v. 3. p. 361--384. 2004.

Looking for Instruction Patterns in the Design of Extensible Processors

Paulo Castro, Edson Borin, Rodolfo Azevedo, Guido Araujo. In Workshop on Application Specific Processors - WASP'04. 2004.

Teaching computer architecture using an architecture description language

Sandro Rigo, Marcio Juliato, Rodolfo Azevedo, Guido Ara\'{u}jo, Paulo Centoducatte. In Proceedings of the 2004 workshop on Computer architecture education: held in conjunction with the 31st International Symposium on Computer Architecture. Munich, Germany. 2004.

Fast Instruction Set Customization

E. Borin, F. Klein, N. Moreano, R. Azevedo, G. Araujo. In ESTImedia 2004: Proceedings of the 2nd Workshop on Embedded Systems for Real-Time Multimedia. p. 53-58. 2004.

ArchC: a systemC-based architecture description language (Best Paper Award)

S. Rigo, G. Araujo, M. Bartholomeu, R. Azevedo. In 16th Symposium on Computer Architecture and High Performance Computing, 2004 - SBAC-PAD 2004. p. 66 - 73. 2004.

Optimizations for compiled simulation using instruction type information

M. Bartholomeu, R. Azevedo, S. Rigo, G. Araujo. In Computer Architecture and High Performance Computing, 2004. SBAC-PAD 2004. 16th Symposium on. p. 74 - 81. 2004.

Multi-profile based code compression

E. Wanderley Netto, R. Azevedo, P. Centoducatte, G. Araujo. In Proceedings of the 41st annual Design Automation Conference. p. 244--249. San Diego, CA, USA. 2004.

Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology

Pablo Viana, Edna Barros, Sandro Rigo, Rodolfo Azevedo, Guido Ara\'{u}jo. In Proceedings of the conference on Design, automation and test in Europe - Volume 1. p. 10734--. 2004.

2003

The ArchC Architecture Description Language

Sandro Rigo, Rodolfo J. Azevedo, Guido Araujo. Technical Report: Institute of Computing, University of Campinas. 2003.

Address register allocation for arrays in loops of embedded programs

Guilherme Ottoni, Guido Araujo. Microelectronics Journal. v. 34. p. 1009 - 1018. 2003.

Improving Offset Assignment through Simultaneous Variable Coalescing (Best Paper Award)

Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers. In Software and Compilers for Embedded Systems. v. 2826. p. 285-297. 2003.

Emulating Operating System Calls in Retargetable ISA Simulators

Marcus Bartholomeu, Sandro Rigo and Rodolfo Azevedo, Guido Araujo. Technical Report: Institute of Computing, University of Campinas. 2003.

Mixed static/dynamic profiling for dictionary based code compression

E. Netto, R. Azevedo, P. Centoducatte, G. Araujo. In International Symposium on System-on-Chip, 2003. p. 159 - 163. 2003.

Exploring memory hierarchy with ArchC

P. Viana, E. Barros, S. Rigo, R. Azevedo, G. Araujo. In 15th Symposium on Computer Architecture and High Performance Computing, 2003. p. 2 - 9. 2003.

2002

Efficient Array Reference Allocation for Loops in Embedded Processors

Guilherme Ottoni, Guido Araujo. In 1st IEEE Workshop on Embedded System Codesign. p. 63--68. 2002.

Global array reference allocation

Guido Araujo, Guilherme Ottoni, Marcelo Silva Cintra. ACM Trans. Des. Autom. Electron. Syst.. v. 7. p. 336--357. 2002.

Datapath merging and interconnection sharing for reconfigurable architectures

Nahri Moreano, Guido Araujo, Zhining Huang, Sharad Malik. In Proceedings of the 15th international symposium on System Synthesis. p. 38--43. Kyoto, Japan. 2002.

2001

Optimal Live Range Merge for Address Register Allocation in Embedded Programs

Guilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik. In Compiler Construction. v. 2027. p. 274-288. 2001.

Array Reference Allocation Using SSA-Form and Live Range Growth

Marcelo Cintra, Guido Araujo. In Languages, Compilers, and Tools for Embedded Systems. v. 1985. p. 48-62. 2001.

Modifying a VLIW Compiler Framework to Implement an Optimizing Compiler for a Fixed Point DSP

S. Rajagopalan, S.P. Rajan, S. Malik, S. Rigo, G. Araujo, S. Rajan. In Proc. of the 5th International Workshop on Software and Compilers for Embedded Systems. v. 2027. p. 1-5. 2001.

Tailoring pipeline bypassing and functional unit mapping to application in clustered VLIW architectures

Marcio Buss, Rodolfo Azevedo, Paulo Centoducatte, Guido Araujo. In Proceedings of the 2001 international conference on Compilers, architecture, and synthesis for embedded systems. p. 141--148. Atlanta, Georgia, USA. 2001.

A retargetable VLIW compiler framework for DSPs with instruction-level parallelism

S. Rajagopalan, S.P. Rajan, S. Malik, S. Rigo, G. Araujo, K. Takayama. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. v. 20. p. 1319 -1328. 2001.

2000

Expression-tree-based algorithms for code compression on embedded RISC architectures

G. Araujo, P. Centoducatte, R. Azevedo, R. Pannain. IEEE Transactions onVery Large Scale Integration (VLSI) Systems. v. 8. p. 530 -533. 2000.

1999

Using Factorization to Compress DSP Programs

Ricardo Pannain, Paulo Centoducatte, Guido Araujo. In 11th SBAC-PAD. p. 223-229. 1999.

Compressed code execution on DSP architectures

P. Centoducatte, G. Araujo, R. Pannain. In 12th International Symposium onSystem Synthesis, 1999. p. 56 -61. 1999.

1998

Code compression based on operand factorization

G. Araujo, P. Centoducatte, M. Cortes, R. Pannain. In 31st Annual ACM/IEEE International Symposium on Microarchitecture, 1998. MICRO-31.. p. 194 -201. 1998.

Code generation for fixed-point DSPs

Guido Araujo, Sharad Malik. ACM Trans. Des. Autom. Electron. Syst.. v. 3. p. 136--161. 1998.

1997

Code Generation Algorithms for Digital Signal Processors

Guido Araujo. In PhD Thesis. Princeton University. 1997.

1996

Code Generation and Optimization Techniques for Embedded Digital Signal Processors

Stan Liao, Srinivas Devadas, Kurt Keutzer, Steve Tjiang, Albert Wang, Guido Araujo, Ashok Sudarsanam, Sharad Malik, Vojin Zivojnovic, Heinrich Meyr. In First SUIF Workshop. 1996.

Instruction set design and optimizations for address computation in DSP architectures

G. Araujo, A. Sudarsanam, S. Malik. In 9th International Symposium onSystem Synthesis. p. 102 -107. 1996.

Using register-transfer paths in code generation for heterogeneous memory-register architectures (Best Paper Award)

Guido Araujo, Sharad Malik, Mike Tien-Chien Lee. In Proceedings of the 33rd annual Design Automation Conference. p. 591--596. Las Vegas, Nevada, United States. 1996.

1995

Challenges in Code Generation For Embedded Processors

G. Araujo, S. Devadas, K. Keutzer, S. Liao, S. Malik, A. Sudarsanam, S. Tjiang, A. Wang. In Code Generation for Embedded Processors. 1995.

Optimal code generation for embedded memory non-homogeneous register architectures

G. Araujo, S. Malik. In Proceedings of the Eighth International Symposium on System Synthesis. p. 36 -41. 1995.

1990

Bidimensional simulation of MOSFETs in thermal equilibrium

Guido Araujo, Petronio Pulino, Bernard Waldman. In The Intrnational Society for Optical Engineering. v. 1405. p. 26-35. 1990.